Texas Instruments /MSP432P411V /LCD_F /LCDCTL

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Interpret as LCDCTL

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (LCDON_0)LCDON 0 (LCDLP_0)LCDLP 0 (LCDSON_0)LCDSON 0 (LCDMXx_0)LCDMXx 0 (LCDPREx_0)LCDPREx 0 (LCDDIVx_0)LCDDIVx0 (LCDSSEL_0)LCDSSEL

LCDLP=LCDLP_0, LCDON=LCDON_0, LCDDIVx=LCDDIVx_0, LCDSSEL=LCDSSEL_0, LCDPREx=LCDPREx_0, LCDMXx=LCDMXx_0, LCDSON=LCDSON_0

Description

LCD_F control

Fields

LCDON

LCD on

0 (LCDON_0): LCD module off

1 (LCDON_1): LCD module on

LCDLP

LCD Low-power Waveform

0 (LCDLP_0): Standard LCD waveforms on segment and common lines selected

1 (LCDLP_1): Low-power LCD waveforms on segment and common lines selected

LCDSON

LCD segments on

0 (LCDSON_0): All LCD segments are off

1 (LCDSON_1): All LCD segments are enabled and on or off according to their corresponding memory location

LCDMXx

LCD mux rate

0 (LCDMXx_0): Static

1 (LCDMXx_1): 2-mux

2 (LCDMXx_2): 3-mux

3 (LCDMXx_3): 4-mux

4 (LCDMXx_4): 5-mux

5 (LCDMXx_5): 6-mux

6 (LCDMXx_6): 7-mux

7 (LCDMXx_7): 8-mux

LCDPREx

LCD frequency pre-scaler

0 (LCDPREx_0): Divide by 1

1 (LCDPREx_1): Divide by 2

2 (LCDPREx_2): Divide by 4

3 (LCDPREx_3): Divide by 8

4 (LCDPREx_4): Divide by 16

5 (LCDPREx_5): Divide by 32

LCDDIVx

LCD frequency divider

0 (LCDDIVx_0): Divide by 1

1 (LCDDIVx_1): Divide by 2

2 (LCDDIVx_2): Divide by 3

3 (LCDDIVx_3): Divide by 4

4 (LCDDIVx_4): Divide by 5

5 (LCDDIVx_5): Divide by 6

6 (LCDDIVx_6): Divide by 7

7 (LCDDIVx_7): Divide by 8

8 (LCDDIVx_8): Divide by 9

9 (LCDDIVx_9): Divide by 10

10 (LCDDIVx_10): Divide by 11

11 (LCDDIVx_11): Divide by 12

12 (LCDDIVx_12): Divide by 13

13 (LCDDIVx_13): Divide by 14

14 (LCDDIVx_14): Divide by 15

15 (LCDDIVx_15): Divide by 16

16 (LCDDIVx_16): Divide by 17

17 (LCDDIVx_17): Divide by 18

18 (LCDDIVx_18): Divide by 19

19 (LCDDIVx_19): Divide by 20

20 (LCDDIVx_20): Divide by 21

21 (LCDDIVx_21): Divide by 22

22 (LCDDIVx_22): Divide by 23

23 (LCDDIVx_23): Divide by 24

24 (LCDDIVx_24): Divide by 25

25 (LCDDIVx_25): Divide by 26

26 (LCDDIVx_26): Divide by 27

27 (LCDDIVx_27): Divide by 28

28 (LCDDIVx_28): Divide by 29

29 (LCDDIVx_29): Divide by 30

30 (LCDDIVx_30): Divide by 31

31 (LCDDIVx_31): Divide by 32

LCDSSEL

Clock source select

0 (LCDSSEL_0): ACLK

1 (LCDSSEL_1): VLOCLK

2 (LCDSSEL_2): REFOCLK

3 (LCDSSEL_3): LFXTCLK

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